Design of Low Power Cmos Based Dual Mode Logic Gates

The CMOS based dual mode logic gates containing two operating modes: 1) static mode 2) dynamic modes. Features of dual mode logic gates are low power dissipation in static mode and high performance in dynamic mode. This methodology is used to minimize the delay and improve the speed of the logic gates and an additional clocked transistor is used in this methodology. It provides the very high level of flexibility. The proposed method is going to be an optimize the power and delay. Sleep transistor allows the path length minimization, delay optimization and delay estimation for Dual mode logic gates. This paper represent the power optimization based on the principles of CMOS based dual mode logic gates. The efficiency of the proposed methodology is shown in a generic 250-nm process. Index Terms Dual mode logic, high performance, minimize delay, logical effort, low power, optimization.